Welcome to the CAD (Computer-Aided Design) lab, where students and researchers can learn and experiment with digital hardware design using two industry-standard hardware description languages: VHDL and Verilog. This lab provides a hands-on experience in designing, simulating, and testing digital circuits using state-of-the-art CAD tools. In this lab, students will learn how to write VHDL and Verilog code to describe the behavior of digital circuits. They will use simulation tools to verify the correctness of their designs before synthesizing them into actual hardware. They will also learn how to use various CAD tools for simulation, synthesis, and place-and-route.