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Mrs. Alka Agrawal

  • Assistant Professor
    Institute of Engineering & Technology

  • Department

    Department of Computer Engineering & Applications

  • Experience

    10.5 Years Teaching experience

  • Qualifications

    • PhD(pursuing): GLA University, Mathura, U.P., India. (Enrolled in year 2016)
      (Area : Adaptive Control System Design using Intelligent Techniques )
    • M.Tech.(2013): Uttar Pradesh Technical University, Lucknow, U.P.(7.67 CGPA)
    • B.Tech.(2006): Uttar Pradesh Technical University, Lucknow, U.P.(77%)
    • 12th(2001): Kendriya Vidyalaya No.3 Jhansi, U.P./C.B.S.E Board(83.2%)
    • 10th(1999): Kendriya Vidyalaya No.3 Jhansi, U.P./C.B.S.E Board(82.4%)

  • Ph.D

    Thesis Supervised

  • Awarded/ Completed-

    Working-

  • Postgraduate

    Thesis Supervised

  • Awarded/ Completed-

    Working-

Journal

  • 01 “Explicit Timing Analysis of Discontinuous RC Global VLSI Interconnect Lines under Ramp Input”, Journal of Electron Devices, Vol. 15, 2012, pp. 1249-1253.
  • 01 Attended and actively participated as organizing committee member in the National Conference on Nano Devices (NCND-2015) held at HCST Mathura
  • 02 Organized the Elocution Contest on green energy ecosystem held on September 2015
  • 03 Participated in two-days workshop on ROBOTICS organized by e-yantra, IIT MUMBAI.
  • 04 Participated in two days Hands on Training on Labview
  • 05 Participated in three days Faculty Development Program on CMOS ICs Methodology of Circuit to Chip Design in association with Entuple Technologies Pvt. Ltd.
  • 06 Participated in three days Faculty Development Program on Numerical Optimization: A practical Approach.
  • 07 Participated in two days hands on training on LaTex

Conferences

  • 01 Agrawal A., Goyal V., Mishra P. (2019) Adaptive Control of a Nonlinear Surge Tank-Level System Using Neural Network-Based PID Controller. In: Malik H., Srivastava S., Sood Y., Ahmad A. (eds) Applications of Artificial Intelligence Techniques in Engineering. Advances in Intelligent Systems and Computing, vol 698. Springer, Singapore
  • 02 “Closed Form Expressions for Extending Step Delay to Ramp Inputs for On-Chip VLSI RC Interconnect” National Conference on Emerging trends in Electrical Instrumentation and Communication Engineering, Agra, April 6-7, 2012
  • 03 “Evaluation of Slew Metric Ramp Inputs for On-Chip VLSI RC Interconnect”, National Conference on Emerging trends in Electrical  Instrumentation and Communication Engineering, Agra, April 6-7, 2012
  • 04 “Elmore's approximations based Explicit Delay and Rise Time Model for Distributed RLC On-Chip VLSI Global Interconnect”, IEEE Symposium on Humanities, Science and Engineering Research, Singapore, 24-27 June 2012, Page(s): 1135 - 113
  • 05 “Moment based Delay Modelling for On-Chip RC Global VLSI Interconnect for Unit Ramp Input” International Joint Conference on Computer Science and Software Engineering (JCSSE) ,Bangkok, Thailand, May 30 2012-June 1 2012, Page(s): 164 – 167

Experience (10.5)

  • 01 Worked in Anand Engineering College, Agra (U.P.) as Lecturer (January 2007-December 2008)
  • 02 Worked in Hindustan College of Science and Technology, Mathura(U.P.) as Assistant Professor (August 2009-December 2016)
  • 03 Working in GLA University, Mathura(U.P.) as Assistant Professor (January 2017-till date)

Subjects Taught

  • 01 Electronics Engineering
  • 02 Analog Integrated Circuit
  • 03 VLSI Design
  • 04 Signals and System