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Mr. Deepak Mittal

Mr. Deepak Mittal

  • Assistant Professor
    Institute of Engineering & Technology
  • Department

    Department of Computer Engineering & Applications
  • Contact Details:

    Email :

    Contact Number :8273093425

  • Experience

    5 years Teaching/Research/Industry experience in

  • Qualifications

    • M.TECH Specialized in VLSI DESIGN from VIT University TAMILNADU Completed May 2015 secured First Division.
    • B.TECH Specialized in Electronics and Telecommunication from IETE New Delhi Completed June 2010 secured First Division.
  • Ph.D

    Thesis Supervised

  • Awarded/ Completed-


  • Postgraduate

    Thesis Supervised

  • Awarded/ Completed-


  • 01Deepak Mittal and Vigneswaran T. Leakage Reduction Using Power Gating Techniques in SRAM Sense Amplifiers, ARPN Journal of Engineering and Applied Sciences, VOL. 10, NO. 7, page no. 2994, APRIL 2015. (Elsevier Journal)
  • 02Deepak Mittal and Vigneswaran. T. Extraordinary Leakage Suppression Techniques in Memory System Design”International Journal of Applied Engineering Research (IJAER), Volume 10, NO. 20, pp.18004- 18007, 2015. (Scopus Indexed Journal)
  • 03Deepak Mittal and Vigneswaran T. “Power and Area Efficient Different Adiabatic Logic Based Adders” International Journal of Applied Engineering Research (IJAER), Volume 10, NO. 20, pp. 15797-15801, 2015. (Scopus Indexed Journal)
  • 04Deepak Mittal and Amit Niranjan “Designing of Multiplexer and De-Multiplexer using different Adiabatic Logic in 90nm Technology” Published in IEEE Explorer and presented in ICCCNT 2018. IISC Banglore.
  • 05Deepak Mittal and Anjan Kumar “Implementation of logic circuits with high speed charge recovery logic” “International Journal of Engineering Research in Computer Science and Engineering”(IJERCSE), PP. 412-416, Vol 5, issue 2, Feb 2018. (UGC Approved Journal)
  • 06Deepak Mittal, V. K. Tomar " Ordinary and Extraordinary Leakage Suppression Techniques for the designing of SRAM Sense Amplifiers "Volume 8, Issue 1, Page no. 1366-1373,  International Journal of Recent Technology and Engineering. (Elsevier Journal)

Life Membership of I.E.T.E.

  • 01Attended 3 days faculty development program on "CMOS ICs Methodology of Circuit to Chip Design" held at GLA University, Mathura from 21st to 23rd February 2019.
  • 02Attended 5 days Faculty Development program on Emerging Trends in Nano Scale Devices and Circuits in NIT Jaipur in April 2018.
  • 03Attended 2 days International Conference On Advances In Computing Applications ICACA 18, NIT Uttarakhand, Srinagar, Uttarakhand, 26-27th February 2018
  • 04Attended 10 days Academy training Program on Digital VLSI Circuit Design in NIT Jaipur in June 2017.
  • 05Attended 3 days Faculty Development Program held at GLA University, Mathura in December 2016.
  • 06Attended 3 days IEEE International conference on Communication, Control and Intelligent systems held at GLA University, Mathura in November 2016
  • 07Attended 2 days National workshop on Tanner EDA software based on Mixed Signal VLSI Design held at GLA University, Mathura in February 2016.
  • 08Attended 2 days IEEE International conference on Communication, Control and intelligent systems held at GLA University, Mathura in November 2015.
  • 09Attended 1 day National Level Technical Symposia on Emerging Trends in Engineering and Technology held at VIT Chennai campus in May 2015.
  • 10Attended 2 days DRDO Sponsored 2nd IEEE International conference on Innovations in Information, Embedded and Communication systems (ICIIECS’15) held at Karpagam College of Engineering, Coimbatore in March 2015.

Teaching Experience Summary

  • 01Currently associated with GLA University as an Assistant Professor in Electronics and Communication Department from July 2015 to till now.
  • 02Six months teaching assistant-ship in VIT University TAMILNADU from July 2014 to December 2014.
  • 03One year Lectureship in “Indian Institute of Aircraft Engineering” MAHIPALPUR, New Delhi from August 2011 to July 2012.

Industry Experience Summary

  • 01Seven months experience in “Akon Electronics India Private Limited” USA based Export Company, BAHADURGARH (Haryana) from September 2012 to March 2013 as a “Testing Engineer”.

Key responsibilities:

  • 01Create product testing procedure as per MO (Manufacturing Order) and ATP (Acceptance Test Procedure) approved by military standard. Create and maintain test and measurement data record as per ATP specifications.